Field Programmable Gate Arrays (FPGAs) represent a group of logic circuits which can be programmed by the user himself. FPGAs contain a multiplicity of configurable logic cells in which signal processing is carried out at the bit level. A configurable logic cell generally comprises a look up table (LUT), which permits the implementation of a Boolean function with N input variables and one output variable. In this case, by means of a multiplexer tree whose branches are fed by bits stored in memory cells, in a work step, a bit is in each case read out in a manner dependent on the N input variables which control the multiplexers. Theoretically, any function can be mapped between the inputs and the output of the look up table. In practice, however, the number of inputs is usually limited to four to five since more complex basic gates are only rarely required.
The automated design of FPGA applications is based on its so called synthesis. In this case, the synthesis tools map a logic function in high level language description, e.g. VHDL (Very high speed integrated circuit Hardware Description Language), onto a plurality of configurable logic cells.
Conventional look up tables with more than three inputs have a high degree of redundancy and, for the most part, unutilized capacity. By way of example, a look up table having four inputs can represent 216=65536 logic functions. However, many of these functions can be traced back to other functions again through permutations of the inputs. Overall, there are 3984 permutation classes of this type in the aforementioned case. However, even this number of functions is generally still too large to enable it to be expediently utilized in the synthesis. For the implementation of the look up table in the logic cell, this means that a relatively large amount of area is required which is ultimately not utilized expediently. Furthermore, as the number of inputs of the logic cell rises, so does the hardware outlay required in order to configure the memory cells of the logic cell.